Last year, Intel already presented plans for two innovations of the x86 platform and instruction set, on which virtually all PC processors (Intel, AMD, China’s Zhaoxin) are based. On the one hand, it was an extension of APX, which overcomes the limitation in the number of working registers and slightly softens ARM’s lead in this discipline, and then AVX10, which is the successor or perhaps a new adaptation of AVX-512. For a long time it was not clear when this paper would come, but now we finally know.
Intel has not yet publicly announced anywhere for which processor generations APX and AVX10 support is planned. Perhaps also because it is not yet certain whether the processors in question will not be affected by a delay. And the company also probably does not want to take the wind out of the sails of previous generations, which do not yet have these innovations. But unofficial targets have already leaked out.
According to an employee (or ex-employee) of the Israeli branch of Intel, who apparently participated in the CPU architectures (Stanislav Shwartsman), Intel plans to incorporate these big news into the processor architecture labeled Panther Cove. The core of Panther Cove is meant to be the next big architectural leap, similar in meaning to the now released Lion Cove. It is interesting that after a long time Intel will change its CPUID from “Family 6”, which had processors practically from Pentium Pro, to “Family 19”. This could perhaps be intended to reflect that this core will be a bigger divide against the past just through these new technologies.
Planned overhaul of the x86 platform
APX is that the processor gets 32 general architecture (i.e. visible from the programmer’s point of view) registers instead of the previous 16. More registers should mean the potential for better performance and is one of the things that RISC processors, and currently ARMv8 in particular, have an advantage in and ARMv9. At the same time, APX should also bring support for conditional operations and three-operand encoding of instructions, when the result will not destructively overwrite one of the inputs.
x86 processors have been using various techniques for a long time to mitigate the limitations that these changes solve (in reality, they have much more registers and use their renaming, and then techniques like store to load forwarding, MOV elimination), but even so, these changes could bring a little better performance . But the software will have to be modified or at least recompiled in order to use APX. We wrote more about this technology here:
AVX10 in turn, it is the successor of the AVX2 and AVX-512 SIMD instructions, which is supposed to be a kind of solution to the problem that Intel made by supporting the 512-bit AVX-512 instructions in a very fragmented way since 2017. At first, they were provided only by server processors, then with the 10nm Ice Lake chips they were also used in laptops (and in the case of Rocket Lake also in desktops), but Intel soon began to produce hybrid processors. Unfortunately, AVX-512 can’t do it with E-Core cores, and that marked the end of his attempts to bring AVX-512 to PCs and laptops (now, paradoxically, AVX-512 offers AMD processors with Zen 4 and Zen 5 cores).
AVX10 solves this with such a compromise that it takes the advanced features of the AVX-512 instructions, but effectively reduces the vector width to only 256 bits like AVX2 (still better than the 128 bits that ARM is stuck at, even with its variable SVE extension , which should theoretically allow for larger widths). AVX10 will also have a 512-bit version, which would be functionally equivalent to AVX-512, but only server processors will support this, while in desktop and notebook processors the processors will have AVX10-256 support, which E-Core cores will also be able to provide (even if 128-bit units). Unfortunately, this risks fragmentation, when developers of programs and games will not be willing to optimize software for 512-bit processors and will be satisfied only with the “baseline” AVX10-256. We wrote more about how this extension is supposed to work here:
Intel has a third innovation or “cleaning” of the x86 platform in its plans, and it is labeled expansion or evolution x86S. This, in turn, is focused more on the system level, starting the operating system and similar low-level mechanisms. This update would simplify the architecture by removing some very old legacy features. Its side effect will be that only new 64-bit operating systems can be run on the processors – unlike APX, x86S actually breaks compatibility with earlier x86 processors, although not fully. At the level of user applications, old 32-bit programs should continue to work, breaking compatibility should only be at the level of the “core” code of operating systems. Should it be necessary to run any older Windows or software, the solution is to be emulation in the future.
Unlike APX and AVX10, however, it is not yet said that x86S will also be part of the Panther Cove core. So this innovation or update of the instruction set can probably be a distant thing. Intel recently published a new draft version of these changes, and it’s possible that this is still a matter of ongoing discussion, and the final form may still change.
Unofficial Tick-Tock 2.0: Panther Cove in two years?
According to Shwartsman, Intel is still essentially continuing something like the tick-tock model of the past, where a major core architecture undergoes major updates every generation — those major upgrades were Sunny Cove, Golden Cove, now Lion Cove, and it’s supposed to be the Panther core Cove. In between, there are generations with minor modifications, which was the core of Willow Cove, Redwood Cove in 4nm Meteor Lake processors (which has some changes against Golden Cove and Raptor Cove, they were analyzed in detail by the website Chips and Cheeseif you’re curious).
Between the current Lion Cove, which will be in Core Ultra 200 processors, and the big Panther Cove upgrade, there is also supposed to be one more core representing a smaller update, called Cougar Cove. This “intermediate core” is to be used in Panther Lake processors, which will be sold as Core Ultra 300, use Intel’s 1.8nm process, but will apparently only be produced for notebooks. This will make this generation quite similar to the Meteor Lake generation.
Therefore, the Panther Cove core will not be in the Panther Lake processors directly (the reason remains over this marking, but it could be explained by the fact that Intel had to postpone the core architecture by a year and it was originally supposed to be in Panther Lake). But it will probably only appear in the following Core Ultra 400 processors, i.e. Nova Lake, which will be a generation for both desktops and laptops, allegedly using TSMC’s 2nm manufacturing process. In addition, the Panther Lake core in a version with 512-bit SIMD units (and AMX support) is supposed to be deployed in Xeon “Diamond Rapids” server processors (there it could possibly be under the name Panther Cove-X), which should be the next generation of Xeons after the now released Xeon 6 “Granite Rapids” processors. According to some information, only the architecture in Xeons may be called “Panther Cove” directly, while in Nova Lake it could be renamed “Coyotte Cove” (probably to avoid confusing the name).
Both Nova Lake and Diamond Rapids should probably be products that will be released in two years – next autumn, the generation of Panther Lake without the Panther Cove core will be released as Core Ultra 300, and Nova Lake as Core Ultra 400 should therefore come sometime in the second mid 2026. Server processors may not come out until a bit later after that.
The year 2026 is therefore the date when APX and AVX10 support could actually appear for the first time. So from Intel. It is not yet clear whether or when AMD plans to adopt these new x86 suite extensions.
Resources: Tom’s Hardware, InstLatX64, Stanislav Shwartsman
Source: www.cnews.cz
