For the segment of computing accelerators used as part of artificial intelligence systems, TSMC’s ability to package a sufficient number of chips using the CoWoS method is of great importance, since in the case of the production of solutions Nvidia remains a bottleneck. The Taiwanese manufacturer intends to actively expand its core capacity not only next year, but also in 2026.
Image Source: TSMC
At the very least, TSMC CEO and Chairman CC Wei explained that the company’s CoWoS chip packaging capabilities will more than double this year compared to last year, and could also double next year. . It is possible, according to the head of the company, that even this rate of expansion will not be enough to satisfy the demand for TSMC’s core services.
If we talk about the economics of the process, TSMC now receives no more than 10% of its revenue from providing chip packaging services, and in the next five years this segment will grow faster than other areas of the company’s activities. So far, it has not been able to reach the average indicators for all segments in terms of profit margins, but the difference is no longer so great. TSMC estimates its share of the global market for chip packaging services at approximately 30%.
According to Money DJ, TSMC has already placed orders for the equipment it will need to package chips until 2026 inclusive. If by the end of this year, TSMC can process 40,000 silicon wafers per month in equivalent terms in the chip packaging direction using the CoWoS method, then next year the volume will double to 80,000 pieces per month. By 2026, the pace of expansion may slow down, ranging from 100 to 120 thousand wafers per month. However, if there is demand, these figures can easily increase to 140 or 150 thousand wafers per month.
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Source: 3dnews.ru
